Low power consumption regulator circuitry

ABSTRACT

Regulator circuitry includes first to third output transistors, a first control transistor and a circuit stage. The first and second output transistors, and the first control transistor have a first channel conductivity type. The second output transistor has a second channel conductivity type. The first and second output transistors have a drain coupled to an output node and a source coupled to a first power supply line. The third output transistor has a drain coupled to the output node and a source coupled to a second power supply line. The circuit stage is configured to drive the gates of the first output transistor, the third output transistor, and the first control transistor based on a specified level of the output voltage.

FIELD

The disclosed technology generally relates to regulator circuitry.

BACKGROUND

Voltage regulators such as linear regulators and low-dropout (LDO)regulators are widely used to generate constant voltages in integratedcircuits (ICs). A voltage regulator may consume considerable powerespecially when driving a large capacitive load, and there is thereforea technical need for providing low power consumption regulators.

SUMMARY

This summary is provided to introduce in a simplified form a selectionof concepts that are further described below in the detaileddescription. This summary is not intended to identify key features oressential features of the claimed subject matter, nor is it intended tolimit the scope of the claimed subject matter.

In one or more embodiments, regulator circuitry is provided. Theregulator circuitry includes a first output transistor of a firstchannel conductivity type, a second output transistor of the firstchannel conductivity type, a third output transistor of a second channelconductivity type opposite to the first channel conductivity type, afirst control transistor of the first channel conductivity type, and acircuit stage. The first output transistor has a drain coupled to anoutput node on which an output voltage is generated and a source coupledto a first power supply line. The second output transistor has a draincoupled to the output node and a source coupled to the first powersupply line. The third output transistor has a drain coupled to theoutput node and a source coupled to a second power supply line. Thefirst control transistor has a gate coupled to a gate of the firstoutput transistor and a source coupled to a gate of the second outputtransistor. The circuit stage is configured to drive the gates of thefirst output transistor, the third output transistor, and the firstcontrol transistor based on a specified level of the output voltage.

In other embodiments, regulator circuitry includes a first outputtransistor of a first channel conductivity type, a second outputtransistor of the first channel conductivity type, a third outputtransistor of a second channel conductivity type opposite to the firstchannel conductivity type, a circuit stage, and first level shiftingcircuitry. The first output transistor has a drain coupled to an outputnode on which an output voltage is generated and a source coupled to afirst power supply line. The second output transistor has a draincoupled to the output node and a source coupled to the first powersupply line. The third output transistor has a drain coupled to theoutput node and a source coupled to a second power supply line. Thecircuit stage is configured to provide a first gate voltage to a gate ofthe first output transistor based on a specified level of the outputvoltage; and provide a second gate voltage to a gate of the third outputtransistor based on the specified level of the output voltage. The firstlevel shifting circuitry is configured to provide a first level-shiftedgate voltage to a gate of the second output transistor, the firstlevel-shifted gate voltage being generated through level shifting of thefirst gate voltage.

In one or more embodiments, a method for operating regulator circuitryis provided. The method includes supplying, based on a specified levelof an output voltage, a first gate voltage to a gate of a first outputtransistor of a first channel conductivity type. The first outputtransistor has a drain coupled to an output node on which the outputvoltage is generated and a source coupled to a first power supply line.The method further includes supplying a first level-shifted gate voltageto a gate of a second output transistor of the first channelconductivity type. The second output transistor has a drain coupled tothe output node and a source coupled to the first power supply line. Thefirst level-shifted gate voltage is generated on a source of a firstcontrol transistor of the first channel conductivity type. The firstcontrol transistor has a gate coupled to the gate of the first outputtransistor. The method further includes supplying, based on thespecified level of the output voltage, a second gate voltage to a gateof a third output transistor of a second channel conductivity typeopposite to the first channel conductivity type. The third outputtransistor has a drain coupled to the output node and a source coupledto a second power supply line.

Other aspects of the embodiments will be apparent from the followingdescription and the appended claims.

BRIEF DESCRIPTION OF DRAWINGS

So that the manner in which the above recited features of the presentdisclosure can be understood in detail, a more particular description ofthe disclosure, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlyexemplary embodiments, and are therefore not to be considered limitingof inventive scope, as the disclosure may admit to other equallyeffective embodiments.

FIG. 1 illustrates an example configuration of regulator circuitry,according to one or more embodiments.

FIG. 2 illustrates an example configuration of an amplifier circuitstage of regulator circuitry, according to one or more embodiments.

FIG. 3A, FIG. 3B, and FIG. 3C illustrate example operations of regulatorcircuitry, according to one or more embodiments.

FIG. 4 illustrates an example configuration of regulator circuitry,according to other embodiments.

FIG. 5 illustrates an example configuration of regulator circuitry,according to still other embodiments.

FIG. 6 illustrates example configurations of a display driver and adisplay panel, according to one or more embodiments.

FIG. 7 illustrates an example configuration of a pixel, according to oneor more embodiments.

FIG. 8 illustrates an example method of operating regulator circuitry,according to one or more embodiments.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements disclosed in oneembodiment may be beneficially utilized in other embodiments withoutspecific recitation. Suffixes may be attached to reference numerals fordistinguishing identical elements from each other. The drawings referredto herein should not be understood as being drawn to scale unlessspecifically noted. Also, the drawings are often simplified and detailsor components omitted for clarity of presentation and explanation. Thedrawings and discussion serve to explain principles discussed below,where like designations denote like elements.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and isnot intended to limit the disclosure or the application and uses of thedisclosure. Furthermore, there is no intention to be bound by anyexpressed or implied theory presented in the preceding background,summary, or the following detailed description.

In the application, the term “coupled” as used means connected directlyto or connected through one or more intervening components or circuits.

Voltage regulators are widely used to generate constant voltages (e.g.,power supply voltages) in ICs. One issue with voltage regulators may bepower consumption. A voltage regulator coupled to a large loadcapacitance may incorporate an output transistor with an increased gatewidth (or an increased transistor size). Such a voltage regulator mayhowever suffer from increased power consumption due to an increasedself-consumption current through the output transistor. The presentdisclosure provides technologies to reduce current consumption ofregulator circuitry.

In one or more embodiments, regulator circuitry includes a first outputtransistor of a first channel conductivity type, a second outputtransistor of the first channel conductivity type, a third outputtransistor of a second channel conductivity type opposite to the firstchannel conductivity type, a first control transistor of the firstchannel conductivity type, and a circuit stage. The first outputtransistor has a drain coupled to an output node on which an outputvoltage is generated and a source coupled to a first power supply line.The second output transistor has a drain coupled to the output node anda source coupled to the first power supply line. The third outputtransistor has a drain coupled to the output node and a source coupledto a second power supply line. The first control transistor has a gatecoupled to a gate of the first output transistor and a source coupled toa gate of the second output transistor. The circuit stage is configuredto drive the gates of the first output transistor, the third outputtransistor, and the first control transistor based on a specified levelof the output voltage. This circuit configuration may reduce the gatewidths of the first and third output transistors, which are primarilyused to maintain the output voltage at the specified level, because thesecond output transistor is configured to drive the output voltage whenthe output voltage deviates from the specified level. The reduction inthe gate widths of the first and third output transistors mayeffectively suppress the self-consumption current of the regulatorcircuitry (e.g., the current through the first and third outputtransistors), contributing to current consumption reduction.

FIG. 1 illustrates an example configuration of regulator circuitry 100,which is configured to generate a constant output voltage Vout on anoutput node 104 based on a reference voltage Vref supplied to an inputnode 102, according to one or more embodiments. The reference voltageVref may indicate a specified level of the output voltage Vout. In oneimplementation, the regulator circuitry 100 may be configured toregulate the output voltage Vout to have the same voltage level as thereference voltage Vref.

In the illustrated embodiment, the regulator circuitry 100 includes anoutput stage 101 and an amplifier circuit stage 106. The output stage101 includes positive-channel metal oxide semiconductor (PMOS) outputtransistors PO1, PO2, a PMOS control transistor P3, negative-channelmetal oxide semiconductor (NMOS) output transistors NO1, NO2, an NMOScontrol transistor N3, and constant current sources 108 and 110. ThePMOS output transistors PO1, PO2, and the PMOS control transistor P3have a positive channel conductivity type (i.e., p-type), and the NMOSoutput transistors NO1, NO2, and the NMOS control transistor N3 have anegative channel conductivity type (i.e., n-type). In FIG. 1 , thecurrents through the PMOS output transistors PO1 and PO2 are indicatedby “IP1” and “IP2”, and the currents through the NMOS output transistorsNO1 and NO2 are indicated by “IN1” and “IN2.” Further, “Iload” indicatesthe load current supplied to or sunk from a load coupled to the outputnode 104. The polarity of the load current Iload is defined as positive(e.g., Iload>0) when the load current Iload is supplied (or goes out) tothe load coupled to the output node 104 and negative (e.g., Iload<0)when the load current Iload is sunk (or comes in) from the load.

The PMOS output transistor PO1 has a source coupled to a high-side powersupply line 112 on which a high-side power source voltage VH isgenerated, a gate coupled to the amplifier circuit stage 106, and adrain coupled to the output node 104. The PMOS control transistor P3 hasa source coupled to the constant current source 108, a gate coupled tothe gate of the output transistor PO1, and a drain coupled to a low-sidepower supply line 114 on which a low-side power source voltage VL lowerthan the high-side power source voltage VH is generated. The low-sidepower source voltage VL may be a circuit ground voltage. The PMOS outputtransistor PO2 has a source coupled to the high-side power supply line112, a gate coupled to the source of the PMOS control transistor P3, anda drain coupled to the output node 104. In various implementations, thePMOS output transistor PO2 has a larger gate width (or a larger size)than the gate width of the PMOS output transistor PO1, which allows thePMOS output transistor PO2 to drive a larger current than the PMOSoutput transistor PO1 for the same gate-source voltage.

The constant current source 108 is coupled between the high-side powersupply line 112 and the source of the PMOS control transistor P3 togenerate a constant current through the PMOS control transistor P3. Theconstant current source 108 and the PMOS control transistor P3collectively operate as first level shifting circuitry configured togenerate and supply a first level-shifted gate voltage to the PMOSoutput transistor PO2. The first level shifting circuitry is configuredgenerate the first level-shifted gate voltage through level shifting ofthe gate voltage of the PMOS output transistor PO1. In oneimplementation, the gate voltage of the PMOS output transistor PO2 ishigher than the gate voltage of the PMOS output transistor PO1, wherethe difference between the gate voltage of the PMOS output transistorPO2 and the gate voltage of the PMOS output transistor PO1 is equal tothe absolute value of the threshold voltage of the PMOS outputtransistor PO1. By the gate voltage of the PMOS transistor PO2 beinghigher than the gate voltage of the PMOS output transistor PO1, thegate-source voltage of the PMOS output transistor PO2 is lower than thegate-source voltage of the PMOS output transistor PO1. In theillustrated embodiment, the constant current source 108 includes a PMOStransistor P4 that has a source coupled to the high-side power supplyline 112, a gate biased with a fixed bias voltage Vbiasp, and a draincoupled to the source of the PMOS control transistor P3.

The NMOS output transistor NO1 has a source coupled to the low-sidepower supply line 114, a gate coupled to the amplifier circuit stage106, and a drain coupled to the output node 104. The NMOS controltransistor N3 has a source coupled to the constant current source 110, agate coupled to the gate of the output transistor NO1, and a draincoupled to the high-side power supply line 112. The NMOS outputtransistor NO2 has a source coupled to the high-side power supply line112, a gate coupled to the source of the NMOS control transistor N3, anda drain coupled to the output node 104. In various implementations, theNMOS output transistor NO2 has a larger gate width (or a larger size)than the gate width of the NMOS output transistor NO1. The larger gatewidth allows the NMOS output transistor NO2 to drive a larger currentthan the NMOS output transistor NO1 for the same gate-source voltage.

The constant current source 110 is coupled between the low-side powersupply line 114 and the source of the NMOS control transistor N3 togenerate a constant current through the NMOS control transistor N3. Theconstant current source 110 and the NMOS control transistor N3collectively operate as second level shifting circuitry configured togenerate and supply a second level-shifted gate voltage to the NMOSoutput transistor NO2. The second level shifting circuitry is configuredto generate the second level-shifted gate voltage through level shiftingof the gate voltage of the NMOS output transistor NO1. In oneimplementation, the gate voltage of the NMOS output transistor NO2 islower than the gate voltage of the NMOS output transistor NO1, where thedifference between the gate voltages of the NMOS transistors NO1 and NO2is equal to the threshold voltage of the NMOS output transistor NO1. Bythe gate voltage of the NMOS output transistor NO2 being lower than thegate voltage of the NMOS output transistor NO1, the gate-source voltageof the NMOS output transistor NO2 is lower than the gate-source voltageof the NMOS output transistor NO1. In the illustrated embodiment, theconstant current source 110 includes an NMOS transistor N4 that has asource coupled to the low-side power supply line 114, a gate biased witha fixed bias voltage Vbiasn, and a drain coupled to the source of theNMOS control transistor N3.

The amplifier circuit stage 106 is configured to drive the gates of thePMOS output transistor PO1, the PMOS control transistor P3, the NMOSoutput transistor NO1, and the NMOS control transistor N3 based on aspecified level of the output voltage Vout. In the illustratedembodiment, the reference voltage Vref is provided to the input node 102to specify the level of the output voltage Vout. In one implementation,the reference voltage Vref has the specified level and the amplifiercircuit stage 106 is configured to drive the gates of the PMOS outputtransistor PO1, the PMOS control transistor P3, the NMOS outputtransistor NO1, and the NMOS control transistor N3 such that the outputvoltage Vout is equal to the reference voltage Vref. It is noted thatthe PMOS output transistor PO1 and the PMOS control transistor P3 areconfigured to receive the same gate voltage from the amplifier circuitstage 106, and the NMOS output transistor NO1 and the NMOS controltransistor N3 are configured to receive the same gate voltage from theamplifier circuit stage 106.

FIG. 2 illustrate an example configuration of the amplifier circuitstage 106, according to one or more embodiments. In the illustratedembodiment, the amplifier circuit stage 106 includes a pair of NMOStransistors N11, N12, a constant current source 122, current mirrors124, 126, and floating current sources 128 and 130.

The NMOS transistors N11, N12, and the constant current source 122 areconfigured to collectively operate as a differential input stageconfigured to generate a pair of currents corresponding to thedifference between the output voltage Vout and the reference voltageVref. The NMOS transistor N11 has a gate coupled to the output node 104to receive the output voltage Vout and the NMOS transistor N12 has agate coupled to the input node 102 to receive the reference voltageVref. The sources of the NMOS transistors N11 and N12 are commonlycoupled to the constant current source 122, which is configured to drawa constant current from the commonly-coupled sources of the NMOStransistors N11 and N12. As a result, the current through the NMOStransistor N11 corresponds to the output voltage Vout and the currentthrough the NMOS transistor N12 corresponds to the reference voltageVref.

The current mirrors 124, 126, the floating current sources 128 and 130are collectively configured as an active load configured to generate thegate voltage of the PMOS output transistor PO1 (which is also providedto the gate of the PMOS control transistor P3) and the gate voltage ofthe NMOS output transistor NO1 (which is also provided to the gate ofthe NMOS control transistor N3).

The current mirror 124 includes PMOS transistors P13 and P14 that havecommonly-coupled gates coupled to the drain of the PMOS transistor P14.The sources of the PMOS transistors P13 and P14 are commonly coupled tothe high-side power supply line 112. The drain of the PMOS transistorP13 is coupled to a node 132 that is coupled to the drain of the NMOStransistor N11, and the drain of the PMOS transistor P14 is coupled to anode 134 that is coupled to the drain of the NMOS transistors N12.

The current mirror 126 includes NMOS transistors N13 and N14 that havecommonly-coupled to the drain of the NMOS transistor N14. The sources ofthe NMOS transistors N13 and N14 are commonly coupled to the low-sidepower supply line 114. The drain of the NMOS transistor N13 is coupledto a node 136, and the drain of the NMOS transistor N14 is coupled to anode 138.

The floating current source 128 is configured to draw a first constantcurrent from the node 132 and supply the first constant current to thenode 136. In one implementation, the floating current source 128includes an NMOS transistor N15 and a PMOS transistor P15. The NMOStransistor N15 has a drain coupled to the node 132, a source coupled tothe node 136, and a gate biased with a fixed bias voltage V_(BN). ThePMOS transistor P15 has a source coupled to the node 132, a draincoupled to the node 136, and a gate biased with a fixed bias voltageV_(BP).

The floating current source 130 is configured to draw a second constantcurrent from the node 134 and supply the second constant current to thenode 138. In one implementation, the floating current source 130includes an NMOS transistor N16 and a PMOS transistor P16. The NMOStransistor N16 has a drain coupled to the node 134, a source coupled tothe node 138, and a gate biased with the fixed bias voltage V_(BN). ThePMOS transistor P16 has a source coupled to the node 134, a draincoupled to the node 138, and a gate biased with the fixed bias voltageV_(BP).

The node 132 of the amplifier circuit stage 106 is coupled to the gatesof the PMOS output transistor PO1 and the PMOS control transistor P3,and the node 136 is coupled to the gates of the NMOS output transistorNO1 and the NMOS control transistor N3. The amplifier circuit stage 106is configured to supply the gate voltages of the PMOS output transistorPO1 and the PMOS control transistor P3 on the node 132 and the gatevoltages of the NMOS output transistor NO1 and the NMOS controltransistor N3 on the node 136 such that the output voltage Vout is equalto the reference voltage Vref.

In other embodiments, the configuration of the amplifier circuit stage106 may be variously modified. In some embodiments, a pair of PMOStransistors having commonly-coupled sources coupled to a constantcurrent source may be used in place of or in addition to the NMOStransistors N11 and N12. In such embodiments, the gates of the PMOStransistors may be coupled to the output node 104 and the input node102, respectively, and the drains of the PMOS transistors may be coupledto the node 136 and the node 138, respectively. In other embodiments, adifferently-configured active load may be used in the amplifier circuitstage 106.

FIGS. 3A, 3B, and 3C illustrates example operations of the regulatorcircuitry 100 illustrated in FIG. 1 , according to one or moreembodiments. When the output voltage Vout is maintained at the specifiedlevel (e.g., the level of the reference voltage Vref), the load currentIload is zero as illustrated in FIG. 3A. In this case, no currents flowthrough the PMOS output transistor PO2 and the NMOS output transistorNO2 as the gate-source voltage of the PMOS output transistor PO2 islower than the gate-source voltage of the PMOS output transistor PO1 andthe gate-source voltage of the NMOS output transistor NO2 is lower thanthe gate-source voltage of the NMOS output transistor NO1. Accordingly,the self-consumption current through the output stage 101 of theregulator circuitry 100 is equal to the current IP1 through the PMOSoutput transistor PO1 (which is equal to the current IN1 through theNMOS output transistor NO1).

When the output voltage Vout becomes higher than the specified level,the regulator circuitry 100 operates as a current sink (i.e., Iload<0)as illustrated in FIG. 3B. In this case, the amplifier circuit stage 106drives the gate of the NMOS output transistor NO1 to increase thegate-source voltage of the NMOS output transistor NO1, which alsoincreases the gate-source voltage of the NMOS output transistor NO2 asthe gate voltage of the NMOS output transistor NO2 is generated throughlevel shifting of the gate voltage of the NMOS output transistor NO1. Inembodiments where the NMOS output transistor NO2 has a sufficientlylarger gate width than the gate width of the NMOS output transistor NO1,the NMOS output transistor NO2 primarily generates the load currentIload sunk from the load coupled to the output node 104 to discharge theload. It is noted that no current flows through the PMOS outputtransistor PO2. Also in this case, the self-consumption current throughthe output stage 101 of the regulator circuitry 100 is equal to thecurrent IP1 through the PMOS output transistor PO1 (which is equal tothe current IN1 through the NMOS output transistor NO1).

When the output voltage Vout becomes lower than the specified level, theregulator circuitry 100 operates as a current source (i.e., Iload>0) asillustrated in FIG. 3C. In this case, the amplifier circuit stage 106drives the gate of the PMOS output transistor PO1 to increase thegate-source voltage of the PMOS output transistor PO1, which alsoincreases the gate-source voltage of the PMOS output transistor PO2 asthe gate voltage of the PMOS output transistor PO2 is generated throughlevel shifting of the gate voltage of the PMOS output transistor PO1. Inembodiments where the PMOS output transistor PO2 has a sufficientlylarger gate width than the gate width of the PMOS output transistor PO1,the PMOS output transistor PO2 primarily generates the load currentIload supplied to the load coupled to the output node 104 to charge theload. It is noted that no current flows through the NMOS outputtransistor NO2. Also in this case, the self-consumption current throughthe output stage 101 of the regulator circuitry 100 is equal to thecurrent IP1 through the PMOS output transistor PO1 (which is equal tothe current IN1 through the NMOS output transistor NO1).

The circuit configuration of the regulator circuitry 100, which operatesas illustrated in FIGS. 3A, 3B, and 3C in one or more embodiments,allows reducing the gate widths of the PMOS output transistor PO1 andthe NMOS output transistor NO1, which are primarily used to maintain theoutput voltage Vout at the specified level (e.g., the level of thereference voltage Vref), since the PMOS output transistor PO2 and theNMOS output transistor NO2 are configured to drive the load currentIload when the output voltage Vout deviates from the specified level.The reduction in the gate widths of the PMOS output transistor PO1 andthe NMOS output transistor NO1 may effectively suppress the currentthrough the PMOS output transistor PO1 and the NMOS output transistorNO1 of the output stage 101, contributing to current consumptionreduction.

The gate widths of the PMOS output transistor PO2 and the NMOS outputtransistor NO2 may be adjusted based on the load capacitance coupled tothe output node 104. The PMOS output transistor PO2 and the NMOS outputtransistor NO2 may be designed to have increased gate widths when alarge load capacitance is anticipated to be coupled to the output node104. The increased gate widths allow the PMOS output transistor PO2 andthe NMOS output transistor NO2 to drive the output voltage Vout to thespecified level with an increased drive capability when the outputvoltage Vout undesirably deviates from the specified level. The increasein the gate widths of the PMOS output transistor PO2 and the NMOS outputtransistor NO2 may allow further reducing the gate widths of the PMOSoutput transistor PO1 and the NMOS output transistor NO1, which maycontribute to further reduction in the self-consumption current of theoutput stage 101.

FIG. 4 illustrates an example configuration of regulator circuitry 100A,according to other embodiments. The regulator circuitry 100A isconfigured similarly to the regulator circuitry 100 illustrated in FIG.1 except for that the PMOS output transistor PO2, the PMOS controltransistor P3, and the constant current source 108 are omitted from theoutput stage, denoted by numeral 101A. The regulator circuitry 100A isconfigured to operate as a current sink when the output voltage Voutbecomes higher than the specified level.

FIG. 5 illustrates an example configuration of regulator circuitry 100B,according to still other embodiments. The regulator circuitry 100B isconfigured similarly to the regulator circuitry 100 illustrated in FIG.1 except for that the NMOS output transistor NO2, the NMOS controltransistor N3, and the constant current source 110 are omitted from theoutput stage, denoted by numeral 101B. The regulator circuitry 100B isconfigured to operate as a current source when the output voltage Voutbecomes lower than the specified level.

FIG. 6 illustrates an example use of regulator circuitry 100 illustratedin FIG. 1 , according to one or more embodiments. In the illustratedembodiment, regulator circuitry 100-1 and regulator circuitry 100-2,which are configured as illustrated in FIG. 1 , are integrated in adisplay driver 200 configured to drive a display panel 300. The displaypanel 300 includes a display area (or active area) 310 and a scan driver320. The display area 310 includes scan lines 312, source lines 314, andpixels 316 (one shown), each coupled to the corresponding scan line 312and source line 314. The scan driver 320 is configured to drive the scanlines 312. The display driver 200 includes a source driver 210configured to drive the source lines 314 based on image datacorresponding to an image to be displayed on the display area 310.

In one implementation, the pixels 316 are each configured to receive ahigh-side power supply voltage ELVDD and a low-side power supply voltageELVSS to operate circuit components incorporated therein. FIG. 7illustrates an example configuration of a pixel 316, according to one ormore embodiments. In the illustrated embodiment, the pixel 316 includesa select transistor 322, a drive transistor 324, a storage capacitor326, and an organic light emitting diode (OLED) 328. In the illustratedembodiment, the select transistor 322 and the drive transistor 324 areconfigured as PMOS thin film transistors. The select transistor 322 hasa first source/drain coupled to the corresponding source line 314, asecond source/drain coupled to the gate of the drive transistor 324, anda gate coupled to the corresponding scan line 312. The drive transistor324 and the OLED 328 are coupled in series between a high-side powersupply line 332 to which the high-side power supply voltage ELVDD isprovided and a low-side power supply line 334 to which the low-sidepower supply voltage ELVSS is supplied. In the illustrated embodiment,the drive transistor 324 has a source coupled to the high-side powersupply line 332 and a drain coupled to the OLED 328. The OLED 328 has ananode coupled to the drain of the drive transistor 324 and a cathodecoupled to the low-side power supply line 334. The storage capacitor 326is coupled between the gate and source of the drive transistor 324. Itis noted that the configuration of the pixel 316 may be variouslymodified, not limited to the illustrated example.

In the embodiment illustrated in FIG. 6 , the regulator circuitry 100-1is configured to generate and supply the high-side power supply voltageELVDD to the display panel 300, and the regulator circuitry 100-2 isconfigured to generate and supply the low-side power supply voltageELVSS to the display panel 300. The use of the regulator circuitry 100-1and 100-2 may effectively reduce current consumption of the displaydriver 200. In other embodiments, the regulator circuitry 100Billustrated in FIG. 5 may be used as the regulator circuitry 100-1 togenerate the high-side power supply voltage ELVDD. In still otherembodiments, the regulator circuitry 100A illustrated in FIG. 4 may beused as the regulator circuitry 100-2 to generate the low-side powersupply voltage ELVSS.

Method 800 of FIG. 8 illustrates steps for operating regulator circuitry(e.g., the regulator circuitry 100 illustrated in FIGS. 1, 2, 4 and 5 ).It is noted that one or more of the steps illustrated in FIG. 8 may beomitted, repeated, and/or performed in a different order than the orderillustrated in FIG. 8 . It is further noted that two or more steps maybe implemented at the same time.

The method includes supplying, based on a specified level of an outputvoltage (e.g., the output voltage Vout), a first gate voltage to a gateof a first output transistor (e.g., the PMOS output transistor PO1 orthe NMOS output transistor NO1) of a first channel conductivity type atstep 802. The first output transistor has a drain coupled to an outputnode (e.g., the output node 104) on which the output voltage isgenerated and a source coupled to a first power supply line (e.g., thehigh-side power supply line 112 or the low-side power supply line 114).The method further includes supplying a first level-shifted gate voltageto a gate of a second output transistor (e.g., the PMOS outputtransistor PO2 or the NMOS output transistor NO2) of the first channelconductivity type at step 804. The second output transistor has a draincoupled to the output node and a source coupled to the first powersupply line. The first level-shifted gate voltage is generated on asource of a first control transistor (e.g., the PMOS control transistorP3 or the NMOS control transistor N3) of the first channel conductivitytype. The first control transistor has a gate coupled to the gate of thefirst output transistor. The method further includes supplying, based onthe specified level of the output voltage, a second gate voltage to agate of a third output transistor (e.g., the NMOS output transistor NO1or the PMOS output transistor PO1) of a second channel conductivity typeopposite to the first channel conductivity type at step 806. The thirdoutput transistor has a drain coupled to the output node and a sourcecoupled to a second power supply line (e.g., the low-side power supplyline 114 or the high-side power supply line 112.)

While many embodiments have been described, those skilled in the art,having benefit of this disclosure, will appreciate that otherembodiments can be devised which do not depart from the scope.Accordingly, the scope of the invention should be limited only by theattached claims.

What is claimed is:
 1. Regulator circuitry, comprising: a first outputtransistor of a first channel conductivity type, the first outputtransistor having a drain coupled to an output node on which an outputvoltage is generated and a source coupled to a first power supply line;a second output transistor of the first channel conductivity type, thesecond output transistor having a drain coupled to the output node and asource coupled to the first power supply line, wherein a gate width ofthe second output transistor is larger than a gate width of the firstoutput transistor; a third output transistor of a second channelconductivity type opposite to the first channel conductivity type, thethird output transistor having a drain coupled to the output node and asource coupled to a second power supply line; a first control transistorof the first channel conductivity type, the first control transistorhaving a gate coupled to a gate of the first output transistor and asource coupled to a gate of the second output transistor; and a circuitstage configured to drive the gates of the first output transistor, thethird output transistor, and the first control transistor based on aspecified level of the output voltage.
 2. The regulator circuitry ofclaim 1, wherein the first control transistor further has a draincoupled to the second power supply line.
 3. The regulator circuitry ofclaim 1, wherein the first channel conductivity type is a negativechannel conductivity type, wherein the second channel conductivity typeis a positive channel conductivity type, wherein a first power supplyvoltage is provided to the first power supply line, and wherein a secondpower supply voltage higher than the first power supply voltage isprovided to the second power supply line.
 4. The regulator circuitry ofclaim 1, wherein the first channel conductivity type is a positivechannel conductivity type, wherein the second channel conductivity typeis a negative channel conductivity type, wherein a first power supplyvoltage is provided to the first power supply line, and wherein a secondpower supply voltage lower than the first power supply voltage isprovided to the second power supply line.
 5. The regulator circuitry ofclaim 1, further comprising: a fourth output transistor of the secondchannel conductivity type, the fourth output transistor having a draincoupled to the output node; and a second control transistor of thesecond channel conductivity type, the second control transistor having agate coupled to a gate of the third output transistor, and a sourcecoupled to a gate of the fourth output transistor.
 6. The regulatorcircuitry of claim 5, wherein the circuit stage is further configured todrive the gate of the third output transistor and the gate of the secondcontrol transistor based on the specified level of the output voltage.7. The regulator circuitry of claim 5, wherein a gate width of thefourth output transistor is larger than a gate width of the third outputtransistor.
 8. The regulator circuitry of claim 5, further comprising: afirst constant current source configured to generate a first constantcurrent through the first control transistor; and a second constantcurrent source configured to generate a second constant current throughthe second control transistor.
 9. The regulator circuitry of claim 5,wherein the first control transistor further has a drain coupled to thesecond power supply line, and wherein the second control transistorfurther has a drain coupled to the first power supply line.
 10. Theregulator circuitry of claim 5, wherein the first channel conductivitytype is a negative channel conductivity type, wherein the second channelconductivity type is a positive channel conductivity type, wherein afirst power supply voltage is provided to the first power supply line,and wherein a second power supply voltage is higher than the first powersupply voltage is provided to the second power supply line. 11.Regulator circuitry, comprising: a first output transistor of a firstchannel conductivity type, the first output transistor having a draincoupled to an output node on which an output voltage is generated and asource coupled to a first power supply line; a second output transistorof the first channel conductivity type, the second output transistorhaving a drain coupled to the output node and a source coupled to thefirst power supply line; a third output transistor of a second channelconductivity type opposite to the first channel conductivity type, thethird output transistor having a drain coupled to the output node and asource coupled to a second power supply line; a first control transistorof the first channel conductivity type, the first control transistorhaving a gate coupled to a gate of the first output transistor and asource coupled to a gate of the second output transistor; a circuitstage configured to drive the gates of the first output transistor, thethird output transistor, and the first control transistor based on aspecified level of the output voltage; and a first constant currentsource configured to generate a first constant current through the firstcontrol transistor.
 12. Regulator circuitry, comprising: a first outputtransistor of a first channel conductivity type, the first outputtransistor having a drain coupled to an output node on which an outputvoltage is generated and a source coupled to a first power supply line;a second output transistor of the first channel conductivity type, thesecond output transistor having a drain coupled to the output node and asource coupled to the first power supply line; a third output transistorof a second channel conductivity type opposite to the first channelconductivity type, the third output transistor having a drain coupled tothe output node and a source coupled to a second power supply line; acircuit stage configured to: provide a first gate voltage to a gate ofthe first output transistor based on a specified level of the outputvoltage; and provide a second gate voltage to a gate of the third outputtransistor based on the specified level of the output voltage; and firstlevel shifting circuitry configured to provide a first level-shiftedgate voltage to a gate of the second output transistor, the firstlevel-shifted gate voltage being generated through level shifting of thefirst gate voltage.
 13. The regulator circuitry of claim 12, wherein agate width of the second output transistor is larger than a gate widthof the first output transistor.
 14. The regulator circuitry of claim 12,wherein the first channel conductivity type is a negative channelconductivity type, wherein the second channel conductivity type is apositive channel conductivity type, wherein a first power supply voltageis provided to the first power supply line, and wherein a second powersupply voltage higher than the first power supply voltage is provided tothe second power supply line.
 15. The regulator circuitry of claim 12,wherein the first channel conductivity type is a positive channelconductivity type, wherein the second channel conductivity type is annegative channel conductivity type, wherein a first power supply voltageis provided to the first power supply line, and wherein a second powersupply voltage lower than the first power supply voltage is provided tothe second power supply line.
 16. The regulator circuitry of claim 12,further comprising: a fourth output transistor of the second channelconductivity type, the fourth output transistor having a drain coupledto the output node and a source coupled to the second power supply line;and second level shifting circuitry configured to provide a secondlevel-shifted gate voltage to a gate of the fourth output transistor,the second level-shifted gate voltage being generated through levelshifting of the second gate voltage.
 17. The regulator circuitry ofclaim 16, wherein a gate width of the second output transistor is largerthan a gate width of the first output transistor, and wherein a gatewidth of the fourth output transistor is larger than a gate width of thethird output transistor.
 18. A method, comprising: supplying, based on aspecified level of an output voltage, a first gate voltage to a gate ofa first output transistor of a first channel conductivity type, thefirst output transistor having a drain coupled to an output node onwhich the output voltage is generated and a source coupled to a firstpower supply line; supplying a first level-shifted gate voltage to agate of a second output transistor of the first channel conductivitytype, the second output transistor having a drain coupled to the outputnode and a source coupled to the first power supply line, the firstlevel-shifted gate voltage being generated on a source of a firstcontrol transistor of the first channel conductivity type, the firstcontrol transistor having a gate coupled to the gate of the first outputtransistor; and supplying, based on the specified level of the outputvoltage, a second gate voltage to a gate of a third output transistor ofa second channel conductivity type opposite to the first channelconductivity type, the third output transistor having a drain coupled tothe output node and a source coupled to a second power supply line. 19.The method of claim 18, further comprising: supplying a secondlevel-shifted gate voltage to a gate of a fourth output transistor ofthe second channel conductivity type, the fourth output transistorhaving a drain coupled to the output node and a source coupled to thesecond power supply line, the second level-shifted gate voltage beinggenerated on a source of a second control transistor of the secondchannel conductivity type, the second control transistor having a gatecoupled to the gate of the third output transistor.